Commercial microelectronics have higher performance, function, and density compared with microelectronics designed for space and military applications. However, designs for such commercial microelectronics result in failure caused by Single Event Upset (SEU) in space applications. For example, ionizing radiation in space (and ground) based applications directly upset storage circuits, such as SRAMs, register files and flip-flops. Moreover, radiation events in combinational logic create voltage glitches that can be latched. Also, SEUs may cause the circuit to perform incorrect or illegal operations; whereas, an accumulation of radiation over a long period of time may additionally lead to complete device failure.
More specifically, in space applications, the major radiation sources are high-energy protons and high-energy heavy ions (from helium up to about any heavy stable isotope). The high-energy cosmic protons and ions are known to produce secondary fragments which cause SEUs and single event latchups (SELs), as well as total failure resulting from total dose (long accumulation of radiation) in semiconductor ICs. Fluxes of cosmic protons and heavy ions can be estimated by models like Cosmic Ray Effects on Microelectronics (CREME) software packages.
For applications on the ground, a major source of radiation is from neutrons. These terrestrial neutrons interact with the devices and the packaging materials to produce secondary (spallation) ions that cause upsets (mainly single event upsets SEUs). The spectra of the secondary ions depend on the device back end of the line (BEOL) materials. The terrestrial neutron flux has been measured and modeled very accurately. In modern nuclear physics and high-energy physics experiments, man-made radiation environments are often generated near the microelectronics that control the detector systems, because the primary beam produces secondary particles (e.g., protons, heavy ions, pions and other particles) which can cause SEUs and SELs. The designs in this invention will also cover these situations.
These upsets, e.g., SEUs, SELs and total failure, occur in many types of commercial device configurations. In one known device configuration, an SOI series device consists of two FETs laid out side by side, where each FET has its own source and drain diffusion regions and each FET is completely surrounded by oxide regions (STI) (FIG. 9). The drain of one FET (FET1) and the source of the other FET (FET2) are connected together electrically by a conducting material. In such device configuration, a charge build-up can occur at an interface between an oxide (STI) and an SOI due to prolonged radiation exposure (total dose) or a high energy single event. This build-up will eventually change the charge flow at the SOI interface, which can lead to a shift in Vt of the device. If the Vt is allowed to move further enough from the design point, the circuitry can fail to operate. Also, in this device configuration, a high energy particle hitting FET1, in the horizontal direction, can travel through the STI and into the adjacent FET2. If this series-connected device is biased to be in the off state when this happens, the horizontally traveling high energy particle can turn on both FETs simultaneously, and hence change the series-connected device from an off state to an on state, thus causing an error.
Alternatively, in another commercial device configuration (see, FIG. 10), a floating n+ region is provided between two gates for the purposes of isolating each of the gates. In this configuration, two adjacent FETs are laid out side by side, sharing one common diffusion with a floating n+ region. The common diffusion is doped to form a drain of one FET (FET1) and a source of the other FET (FET2). In this configuration, when a high energy particle strikes one of the FETs in a direction more or less perpendicular to the semiconductor surface, the electrons generated in the FET being struck can diffuse readily into the other FET unless the width of the floating n+ region is larger than the hole diffusion length. If this happens when the series-connected device is biased in the off state, the diffusion of holes from the FET being struck into the other FET can cause the other FET to be turned on. The net result is that a series-connected device of this configuration can be turned from an off state into an on state when a high energy particle strikes one of the FETs in a direction more or less perpendicular to the semiconductor surface, unless the floating n+ region has a width larger than the hole diffusion length.
The n+ regions for source and drain have a typical doping concentration of 1E20 cm−3. The corresponding hole diffusion length is about 300 nm, which is quite large compared with the minimum lithography dimensions of modern integrated circuit technology. For example, the most advanced CMOS technology in production has a minimum lithographic dimension of only 45 nm. The net is that the series-connected device configuration shown in FIG. 10 is not totally immune to single event upsets when a high energy particle strikes it in a direction more or less perpendicular to the semiconductor surface, unless the width of the floating n+ region is kept at a dimension larger than 300 nm.
Minimizing the occurrence of such upsets with minimal change to design and process would allow the use of close derivatives of commercial components with close to commercial performance, function, and density with a minimal schedule delay. This is crucial for maintaining strategic differentiation for US defense systems against potential adversaries. However current methods to prevent SEUs and total dose include adding spatial and/or temporal redundancy, so that a single radiation event cannot cause an SEU. The series-connected devices shown in FIGS. 9 and 10 provide built-in redundancy at the device level. As explained in the previous paragraphs, device configuration in FIG. 9 is superior to that in FIG. 10 in minimizing SEUs. Nonetheless, the device configuration in FIG. 9 is still sensitive to SEUs when it is struck by a high energy particle traveling more or less horizontally as illustrated in FIG. 9. Consequently, there is a need to improve the series-connected SOI CMOS devices to improve susceptible to radiation events, including when being hit by high energy particles traveling more or less horizontally.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.